Plasma display panels (hereinafter referred to as PDPs) are a type of flat screen device that is capable of high speed display and can also easily be made in large sizes. As such, PDPs are widely used in a wide variety of fields such as image display apparatuses and advertisement display apparatuses.
FIG. 10 shows a schematic elevation of the structure of a discharge cell that is a unit of discharge in a general AC PDP. A PDP 1x shown in FIG. 10 is composed of a front panel 2 and a back panel 9 sealed together. The front panel 2 includes a front panel glass 3. A plurality of display electrode pairs 6 each composed of a scan electrode 5 and a sustain electrode 4 are disposed on the surface of the front panel glass 3. A dielectric layer 7 and a surface layer 8 are layered in the stated order to cover the display electrode pairs 6. The scan electrode 5 and the sustain electrode 4 are composed of respective transparent electrodes 51 and 41 and bus lines 52 and 42 layered together.
The dielectric layer 7 is made of low-melting glass having a softening point of approximately 550 C.° to 600 C.°, and has a current limiting function that is peculiar to AC PDPs.
The surface layer 8 protects the dielectric layer 7 and the display electrode pairs 6 from ion bombardment caused by plasma discharge. The surface layer 8 also efficiently emits secondary electrons and lowers firing voltage. Generally, magnesium oxide (MgO) that has high secondary electron emission properties, high sputtering resistance, and high optical transparency is used to form the surface layer 8 with a thickness of approximately 0.5 μm to 1 μm using a vacuum deposition method (Patent Documents 1 and 2) or a printing method (Patent Document 3). Note that a protective layer that has the identical structure to the surface layer 8 may be provided in order to ensure secondary electron emission properties and to protect the dielectric layer 7 and the display electrode pairs 6.
The back panel 9 includes a back panel glass 10 and a plurality of data (address) electrodes 11 disposed thereon so as to intersect the display electrode pairs 6 substantially at a right angles. The data electrodes 11 are used for writing image data in the discharge cells. On the back panel glass 10, a dielectric layer 12 made of low-melting glass is disposed to cover the data electrodes 11. Disposed at boundaries between adjacent discharge cells (not illustrated) on the dielectric layer 12 at a predetermined height are barrier ribs 13 made of low-melting glass. More specifically, the barrier ribs 13 are composed of pattern parts 1231 and 1232 that combine to form a lattice pattern to partition a discharge space 15 into the plurality of discharge cells. Phosphor ink of red (R), green (G) and blue (B) is applied to the surface of the dielectric layer 12 and the lateral surfaces of the barrier ribs 13, and baked to form phosphor layers 14 (phosphor layers 14R, 14G and 14B).
The front panel 2 and the back panel 9 are sealed together at edge portions thereof such that the display electrode pairs 6 are orthogonal to the data electrodes 11 via the discharge space 15. In the sealed discharge space 15, a rare gas mixture such as Xe—Ne or Xe—He is enclosed as a discharge gas at some tens of kilopascals. This how the PDP 1x is structured.
In order to display an image on the PDP, the method employed is one that expresses gradations in an image by dividing one field of the image into a plurality of subfields (S.F.) (e.g. intra-field time division grayscale display method).
In view of the need for PDPs to be capable of high-definition display (for full spec high vision television and the like) and to be driven at high speed, research into improving discharge properties of PDPs is being widely carried out. One of the important issues addressed by such research is the prevention and suppression of “discharge delay”.
Discharge delay is a phenomenon of a lag from the rising edge of the driving pulse to when discharge occurs when the PDP is driven at high speed with a narrowed driving pulse. When there is a significant occurrence of discharge delay, discharge becomes less likely to be completed within the width of the applied pulse. As a result, there is a risk that some cells will not be addressed properly, and will therefore fail to light. The likelihood of discharge delay occurring in a cell structure for high-definition display is particularly marked when the PDP is driven at high speed. There is a desire to find a solution to the problem of discharge delay as soon as possible.
The cause of discharge delay is thought to lie principally in the properties of the protective layer. One response has been to attempt to improve the discharge properties of the protective layer by adding a dopant such as Fe, Cr and V or a dopant such as Si and Al to the MgO (Patent Documents 1 and 2). Another response has been to attempt to improve discharge properties of the surface of the protective layer by manufacturing single-crystal particles of MgO using a gas phase method, and providing a layer of the single crystal particles either directly on the dielectric layer, or via an MgO film formed using a thin film method (Patent Document 3). The method disclosed by Patent Document 3 achieves some reduction in discharge delay at low temperature.    Patent Document 1: Japanese Unexamined Patent Application Publication No. H08-236028    Patent Document 2: Japanese Unexamined Patent Application Publication No. H10-334809    Patent Document 3: Japanese Unexamined Patent Application Publication No. 2006-173018    Patent Document 4: Japanese Unexamined Patent Application Publication No. 2006-147417    Patent Document 5: Japanese Unexamined Patent Application Publication No. S64-28273